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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TLV760 snvsav1 ? june 2017 TLV760 100-ma, 30-v, fixed-output, linear-voltage regulator 1 1 features 1 ? wide input voltage range up to 30 v ? output current up to 100 ma ? available in fixed output voltage 3.3-v, 5-v, 12-v and 15-v versions ? operating junction temperature ? 40 c to +125 c ? stable with ceramic capacitors greater than or equal to 0.1 f ? active thermal protection and current limit 2 applications ? post regulator for switching dc-dc converter ? bias supply for digital and analog circuits ? home appliances ? power tools ? factory and building automation 3 description the TLV760 is an integrated linear-voltage regulator featuring operation from an input as high as 30 v. the TLV760 has a maximum dropout of 1.2 v at the full 100-ma load across operating temperature. standard packaging for the TLV760 is the 3-pin sot- 23 package. the TLV760 is available in 3.3 v, 5 v, 12 v and 15 v. the sot-23 packaging of the TLV760 series allows the device to be used in space-constrained applications. the TLV760 is a small size alternative to lm78lxx series and similar devices. the TLV760 is designed to bias digital and analog circuits in applications that are subject to voltage transients and spikes up to 30 v ? for example, appliances and automation applications. the device has robust internal thermal protection, which protects itself from potential damage caused by conditions like short to ground, increases in ambient temperature, high load, or high dropout events. device information (1) part number package body size (nom) TLV760 sot-23 (3) 2.92 mm 1.30 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. space space space typical application circuit TLV760 in out gnd c out c in v in = 5 v v out = 3.3 v 0.1 f 0.1 f copyright ? 2017, texas instruments incorporated productfolder ordernow technical documents tools & software support &community
2 TLV760 snvsav1 ? june 2017 www.ti.com product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 typical characteristics .............................................. 6 7 detailed description .............................................. 9 7.1 overview ................................................................... 9 7.2 functional block diagram ......................................... 9 7.3 feature description ................................................... 9 7.4 device functional modes ........................................ 10 8 application and implementation ........................ 11 8.1 application information ............................................ 11 8.2 typical application ................................................. 12 9 power supply recommendations ...................... 14 10 layout ................................................................... 14 10.1 layout guidelines ................................................. 14 10.2 layout example .................................................... 14 11 device and documentation support ................. 15 11.1 device support .................................................... 15 11.2 receiving notification of documentation updates 15 11.3 community resources .......................................... 15 11.4 trademarks ........................................................... 15 11.5 electrostatic discharge caution ............................ 15 11.6 glossary ................................................................ 15 12 mechanical, packaging, and orderable information ........................................................... 16 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes june 2017 * initial release
3 TLV760 www.ti.com snvsav1 ? june 2017 product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) see external capacitors for more details. 5 pin configuration and functions dbz package 3-pin sot-23 top view pin functions pin i/o description no. name 1 out o input voltage supply ? ti recommends a capacitor of value greater than 0.1 f at the input. (1) 2 in i output voltage, a ceramic capacitor greater than or equal to 0.1 f is need for the stability of the device. (1) 3 gnd ? common ground
4 TLV760 snvsav1 ? june 2017 www.ti.com product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings (1) may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) see recommended operating conditions section for more details. 6 specifications 6.1 absolute maximum ratings (1) min max unit input voltage (in to gnd) ? 0.3 35 v output voltage (out) v in + 0.3 v output current internally limited (2) ma junction temperature ? 40 150 c storage temperature, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit maximum input voltage (in to gnd) 30 v output current (i out ) 100 ma input and output capacitor (c out ) 0.1 f junction temperature, t j ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) TLV760 unit dbz (sot-23) 3 pins r ja junction-to-ambient thermal resistance 275.2 c/w r jc(top) junction-to-case (top) thermal resistance 92.8 c/w r jb junction-to-board thermal resistance 56.8 c/w jt junction-to-top characterization parameter 2.9 c/w jb junction-to-board characterization parameter 55.6 c/w
5 TLV760 www.ti.com snvsav1 ? june 2017 product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.5 electrical characteristics typical and other limits apply for t a = t j = 25 c, v out(nom) = 3.3 v, 5 v, 12 v, and 15 v, unless otherwise specified. parameter test conditions min typ max unit v out output voltage accuracy v in = v out(nom) + 1.5 v, 1 ma i out 100 ma ? 4% 4% v v in = v out(nom) + 1.5 v, 1 ma i out 100 ma, ? 40 c t j 125 c ? 5% 5% v ( vin) line regulation v out(nom) + 1.5 v v in 30 v i out = 1 ma , ? 40 c t j 125 c v out(nom) = 3.3 v, 5 v 10 30 mv v out(nom) = 12 v, 15 v 14 45 v ( iout) load regulation v in =v out(nom) + 1.5 v , 10 ma i out 100 ma, ? 40 c t j 125 c v out(nom) = 3.3 v, 5 v 20 45 mv v out(nom) = 12 v, 15 v 45 80 i gnd ground pin current v out(nom) + 1.5 v v in 30 v, no load, ? 40 c t j 125 c 2 5 ma v do dropout voltage i out = 10 ma 0.7 0.9 v i out = 10 ma , ? 40 c t j 125 c 1 i out = 100 ma 0.9 1.1 i out = 100 ma, ? 40 c t j 125 c 1.2 t sd thermal shutdown temperature 150 c
6 TLV760 snvsav1 ? june 2017 www.ti.com product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.6 typical characteristics unless indicated otherwise, v in = v nom + 1.5 v, c in = 0.1 f, c out = 0.1 f, and t a = 25 c. figure 1. dropout voltage vs load current figure 2. dropout voltage vs junction temperature figure 3. ground pin current vs input voltage figure 4. ground pin current vs input voltage figure 5. ground pin current vs load current figure 6. ground pin current vs junction temperature
7 TLV760 www.ti.com snvsav1 ? june 2017 product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) unless indicated otherwise, v in = v nom + 1.5 v, c in = 0.1 f, c out = 0.1 f, and t a = 25 c. figure 7. input current vs input voltage figure 8. input current vs input voltage figure 9. output voltage vs input voltage figure 10. output voltage vs input voltage figure 11. output short-circuit current figure 12. output short-circuit current
8 TLV760 snvsav1 ? june 2017 www.ti.com product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) unless indicated otherwise, v in = v nom + 1.5 v, c in = 0.1 f, c out = 0.1 f, and t a = 25 c. figure 13. power supply rejection ratio figure 14. power supply rejection ratio figure 15. dc load regulation v out (red) = 3.3 v i out (black) = 100ma figure 16. short-circuit current vs input voltage c in = 1 f c out = 0.1 f v out = 3.3 v figure 17. output spectral noise density vs frequency frequency (hz) output noise voltage (uv/sqrt hz) 10 100 1k 10k 100k 1m 10m 0.005 0.01 0.1 1 2 d002d002 3.3 v 0 ma 3.3 v 10 ma 3.3 v 100 ma v in (v) i out (ma) 5.8 8.3 10.8 13.3 15.8 18.3 20.8 23.3 25.7 0 20 40 60 80 100 120 d001 v out (v) 0 0.5 1 1.5 2 2.5 3 3.5
9 TLV760 www.ti.com snvsav1 ? june 2017 product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 detailed description 7.1 overview the TLV760 is an integrated linear-voltage regulator with inputs that can be as high as 30 v. the TLV760 features quasi ldo architecture , which allows the usage of low esr capacitors at the output. a ceramic capacitor with a capacitance value greater than or equal to 0.1 f is adequate to keep the linear regulator in stable operation. the device has a rugged active junction thermal protection mechanism. 7.2 functional block diagram 7.3 feature description 7.3.1 thermal protection the TLV760 contains an active thermal protection mechanism, which limits the junction temperature to 150 c. this protection comes into action when the thermal junction temperature of the device tries to exceed 150 c. the output current of the device is limited or folded back to maintain the junction temperature. the thermal protection follows equation 1 where ? p d = (v in ? v out )i out ? t j is the junction temperature ? r ja is the junction-to-ambient thermal resistance (1) when a high drop out condition occurs resulting in higher power dissipation across the device the output current is limited to maintain a constant junction temperature of 150 c. this rugged feature protects the device from higher power dissipation applications as well as the short to ground at the output. this internal protection circuitry of TLV760 is intended to protect the devices against thermal overload conditions. the circuitry is not intended to replace proper heat sinking. continuously running the TLV760 into thermal protection degrades device reliability. for reliable operation, limit junction temperature to a maximum of 125 c. to estimate the thermal margin in a given layout, increase the ambient temperature until the thermal protection is triggered using worst case load and highest input voltage conditions. d j a ja p (t t ) / r t current limit and thermal protection bandgap reference in out gnd copyright ? 2017, texas instruments incorporated
10 TLV760 snvsav1 ? june 2017 www.ti.com product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) 7.3.2 dropout voltage the TLV760 is a bipolar device with quasi ldo architecture . being a bipolar device the dropout voltage of the device does not change significantly with output load current. the device has a maximum dropout across temperature of 1.2 v at 100-ma load current, which is a significant improvement over the traditional lm78lxx devices. 7.4 device functional modes 7.4.1 normal operation the TLV760 operates with an input up to 30 v. its tiny sot-23 package and quasi-ldo architecture makes it suitable for providing a very tiny 100-ma bias supply. the device regulates to the nominal output voltage when all of the following conditions are met. ? the input voltage is greater than the nominal output voltage plus the dropout voltage (v out(nom) + v do ). ? the output current is less than or equal to 100 ma. ? the device junction temperature is less than the thermal protection temperature of 150 c.
11 TLV760 www.ti.com snvsav1 ? june 2017 product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the TLV760 is a fixed output device which need only input and output capacitors to function. this section discusses the key aspects to implement this linear regulator in typical applications. 8.1.1 fixed output TLV760 comes in fixed output voltage options, 3.3 v, 5 v, 12 v and 15 v. to ensure the proper regulated output, the input voltage should be greater than v out(nom) + v do . 8.1.2 external capacitors 8.1.2.1 input and output capacitor requirements a minimum input and output capacitance value of 0.1 f is required for stability and adequate transient performance. there is no specific equivalent series resistance (esr) limitation, although excessively high esr compromises transient performance. there is no specific limitation on a maximum capacitance value on the input or the output. however while selecting a capacitor, derating factors on the capacitance value should be considered. use c0g, x7r, or x5r-type ceramic capacitors because these capacitors have minimal variation in capacitance value and esr over temperature. 8.1.2.2 load-step transient response the load-step transient response is the output voltage response by the linear regulator to a step change in load current. the depth of charge depletion immediately after the load step is directly proportional to the amount of output capacitance. however, larger output capacitances decrease any voltage dip or peak occurring during a load step, the control-loop bandwidth is also decreased, thereby slowing the response time. ti recommends to optimally scale output capacitors for a specific application and test for the output load transients. 8.1.3 power dissipation proper consideration should be given to device power dissipation, location of the circuit on the printed circuit board (pcb), and correct sizing of the thermal plane to ensure the device reliability. the pcb area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses. to first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. power dissipation can be calculated using the thermal protection follows equation 1 : where ? p d = (v in ? v out )i out ? t j is the junction temperature ? r ja is the junction-to-ambient thermal resistance (2) thus, at a given load current, input and output voltage, maximum power dissipation determines the maximum allowable ambient temperature (t a ) for the device, and vice versa. power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (r ja ) of the combined pcb and device package and the temperature of the ambient air (t a ). r ja is highly dependent on the heat-spreading capability built into the particular pcb design, and therefore varies according to the total copper area, copper weight, and location of the planes. the r ja recorded in thermal information is determined by the jedec standard, pcb, and copper-spreading area and is only used as a relative measure of package thermal performance. d j a ja p (t t ) / r t
12 TLV760 snvsav1 ? june 2017 www.ti.com product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated application information (continued) TLV760 integrates a rugged protection where the t j is limited to 150 c. the maximum power dissipation depends on the ambient temperature and can be calculated using p d = (t j ? t a ) / r ja , for example, substituting the absolute maximum junction temperature, 150 c for t j , 50 c for t a , and 275.2 c/w for r ja , the maximum power that can be dissipated is 363 mw. more power can be safely dissipated at lower ambient temperatures. less power can be safely dissipated at higher ambient temperatures. the power dissipation can be increased by 3.6 mw for each c below 50 c ambient. it must be derated by 3.6 mw for each c above 50 c ambient. proper heat sinking enables the safe dissipation of more power. 8.2 typical application figure 18. typical appication for the 5-v option 8.2.1 design requirements for typical TLV760 applications, use the parameters in table 1 . table 1. design parameters design parameter example value input voltage 6.5 v output voltage 5 v output current 100 ma 8.2.2 detailed design procedure the output for TLV76050 is internally set to 5 v. input and output capacitors can be selected in accordance with the external capacitors . ceramic capacitances of 0.1 f for both input and output are selected. see the layout section for an example of how to pcb layout the TLV760 to achieve best performance. TLV760 in out gnd c out c in v in = 6.5 v v out = 5 v 0.1 f 0.1 f copyright ? 2017, texas instruments incorporated
13 TLV760 www.ti.com snvsav1 ? june 2017 product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.3 application curves unless indicated otherwise, v in = 6.5 v, v out = 5 v, c out = 0.1 f, and t a = 25 c. figure 19. line transient response figure 20. line transient response figure 21. load transient response figure 22. load transient response figure 23. load transient response figure 24. load transient response
14 TLV760 snvsav1 ? june 2017 www.ti.com product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 power supply recommendations the TLV760 is designed to operate from input voltage up to 30 v. if the input power supply has ripples, additional input and output capacitors with low esr can help improve the psrr at higher frequencies. 10 layout 10.1 layout guidelines general guidelines for linear regulator designs are to place all circuit components on the same side of the circuit board and as near as practical to the respective TLV760 pin connections. place ground return connections to the input and output capacitors, and to the TLV760 ground pin as close as possible to each other, connected by a wide, component-side, copper surface. the use of vias and long traces to create TLV760 circuit connections is strongly discouraged and negatively affects system performance. use a ground reference plane, either embedded in the pcb itself or located on the bottom side of the pcb opposite the components. this reference plane serves to assure accuracy of the output voltage and to shield noise; it behaves similarly to a thermal plane to spread heat from the linear regulator. in most applications, this ground plane is necessary to meet thermal requirements. 10.2 layout example figure 25. layout guideline for TLV760 v out v in gnd plane 3 1 2 c out c in
15 TLV760 www.ti.com snvsav1 ? june 2017 product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) for the most current package and ordering information see the package option addendum at the end of this document, or see the device product folder at www.ti.com . 11 device and documentation support 11.1 device support 11.1.1 related documentation for related documentation see the following: an-1148 linear regulators: theory of operation and compensation 11.1.2 spice models computer simulation of circuit performance using spice is often useful when analyzing the performance of analog circuits and systems. a spice model for the TLV760 is available through the TLV760 product folder under simulation models. 11.1.3 device nomenclature table 2. ordering information (1) product description TLV760 xxyyyz xx is the voltage designator yyy is the package designator. z is the package quantity. 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
16 TLV760 snvsav1 ? june 2017 www.ti.com product folder links: TLV760 submit documentation feedback copyright ? 2017, texas instruments incorporated 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 1-jul-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TLV76012dbzr active sot-23 dbz 3 3000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 18g TLV76012dbzt active sot-23 dbz 3 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 18g TLV76015dbzr active sot-23 dbz 3 3000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 18c TLV76015dbzt active sot-23 dbz 3 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 18c TLV76033dbzr active sot-23 dbz 3 3000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 18h TLV76033dbzt active sot-23 dbz 3 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 18h TLV76050dbzr active sot-23 dbz 3 3000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 18i TLV76050dbzt active sot-23 dbz 3 250 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 18i (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
package option addendum www.ti.com 1-jul-2017 addendum-page 2 (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TLV76012dbzr sot-23 dbz 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 q3 TLV76012dbzt sot-23 dbz 3 250 178.0 8.4 3.3 2.9 1.22 4.0 8.0 q3 TLV76015dbzr sot-23 dbz 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 q3 TLV76015dbzt sot-23 dbz 3 250 178.0 8.4 3.3 2.9 1.22 4.0 8.0 q3 TLV76033dbzr sot-23 dbz 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 q3 TLV76033dbzt sot-23 dbz 3 250 178.0 8.4 3.3 2.9 1.22 4.0 8.0 q3 TLV76050dbzr sot-23 dbz 3 3000 178.0 8.4 3.3 2.9 1.22 4.0 8.0 q3 TLV76050dbzt sot-23 dbz 3 250 178.0 8.4 3.3 2.9 1.22 4.0 8.0 q3 package materials information www.ti.com 21-jun-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TLV76012dbzr sot-23 dbz 3 3000 210.0 185.0 35.0 TLV76012dbzt sot-23 dbz 3 250 210.0 185.0 35.0 TLV76015dbzr sot-23 dbz 3 3000 210.0 185.0 35.0 TLV76015dbzt sot-23 dbz 3 250 210.0 185.0 35.0 TLV76033dbzr sot-23 dbz 3 3000 210.0 185.0 35.0 TLV76033dbzt sot-23 dbz 3 250 210.0 185.0 35.0 TLV76050dbzr sot-23 dbz 3 3000 210.0 185.0 35.0 TLV76050dbzt sot-23 dbz 3 250 210.0 185.0 35.0 package materials information www.ti.com 21-jun-2017 pack materials-page 2
4203227/c
www.ti.com package outline c typ 0.20 0.08 0.25 2.64 2.10 1.12 max typ 0.10 0.01 3x 0.5 0.3 typ 0.6 0.2 1.9 0.95 typ-8 0 a 3.04 2.80 b 1.4 1.2 (0.95) sot-23 - 1.12 mm max height dbz0003a small outline transistor 4214838/c 04/2017 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. reference jedec registration to-236, except minimum foot length. 0.2 c a b 1 3 2 index area pin 1 gage plane seating plane 0.1 c scale 4.000
www.ti.com example board layout 0.07 max all around 0.07 min all around 3x (1.3) 3x (0.6) (2.1) 2x (0.95) (r0.05) typ 4214838/c 04/2017 sot-23 - 1.12 mm max height dbz0003a small outline transistor notes: (continued) 4. publication ipc-7351 may have alternate designs. 5. solder mask tolerances between and around signal pads can vary based on board fabrication site. symm land pattern example scale:15x pkg 1 3 2 solder mask opening metal under solder mask solder mask defined metal solder mask opening non solder mask defined (preferred) solder mask details
www.ti.com example stencil design (2.1) 2x(0.95) 3x (1.3) 3x (0.6) (r0.05) typ sot-23 - 1.12 mm max height dbz0003a small outline transistor 4214838/c 04/2017 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 7. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 thick stencil scale:15x symm pkg 1 3 2
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